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rail-to-rail, very fast, 2.5 v to 5.5 v, single-supply ttl/cmos comparator adcmp603 features functional block diagram v p noninverting input v n inverting input s dn input q output q output v cci v cco le/hys input 05915-001 adcmp603 ttl fully specified rail to rail at v = 2.5 v to 5.5 v cc input common-mode voltage from ?0.2 v to v + 0.2 v cc low glitch cmos-/ttl-compatible output stage complementary outputs 3.5 ns propagation delay 12 mw at 3.3 v shutdown pin single-pin control for programmable hysteresis and latch power supply rejection > 50 db ?40c to +125c operation applications figure 1. high speed instrumentation clock and data signal restoration logic level shifting or translation pulse spectroscopy high speed line receivers threshold detection peak and zero-crossing detectors high speed trigger circuitry pulse-width modulators current-/voltage-controlled oscillators automatic test equipment (ate) general description the device passes 4.5 kv hbm esd testing and the absolute maximum ratings include current limits for all pins. the adcmp603 is a very fast comparator fabricated on xfcb2, an analog devices, inc. proprietary process. this comparator is exceptionally versatile and easy to use. features include an input range from v the complementary ttl-/cmos-compatible output stage is designed to drive up to 5 pf with full timing specs and to degrade in a graceful and linear fashion as additional capacitance is added. the comparator input stage offers robust protection against large input overdrive, and the outputs do not phase reverse when the valid input signal range is exceeded. latch and programmable hysteresis features are also provided with a unique single-pin control option. ? 0.5 v to v ee cc + 0.2 v, low noise complementary ttl-/cmos-compatible output drivers, latch inputs with adjustable hysteresis and a shutdown input. the device offers 3.5 ns propagation delay with 10 mv overdrive on 4 ma typical supply current. a flexible power supply scheme allows the device to operate with a single +2.5 v positive supply and a ?0.5 v to +2.8 v input signal range up to a +5.5 v positive supply with a ?0.5 v to +5.8 v input signal range. split input/output supplies with no sequencing restrictions support a wide input signal range while still allowing independent output swing control and power savings. the adcmp603 is available in a 12-lead lfcsp package. rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved.
adcmp603 rev. 0 | page 2 of 16 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical characteristics ............................................................. 3 timing information ......................................................................... 5 absolute maximum ratings ............................................................ 6 thermal resistance ...................................................................... 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 8 application information ................................................................ 10 power/ground layout and bypassing ..................................... 10 ttl-/cmos-compatible output stage ................................. 10 using/disabling the latch feature ........................................... 10 optimizing performance ........................................................... 11 comparator propagation delay dispersion ........................... 11 comparator hysteresis .............................................................. 11 crossover bias point .................................................................. 12 minimum input slew rate requirement ................................ 12 typical application circuits ......................................................... 13 outline dimensions ....................................................................... 14 ordering guide .......................................................................... 14 revision history 10/06revision 0: initial version
adcmp603 rev. 0 | page 3 of 16 specifications electrical characteristics v cci = v cco = 2.5 v, t a = 25c, unless otherwise noted. table 1. parameter symbol conditions min typ max unit dc input characteristics voltage range v p , v n v cc = 2.5 v to 5.5 v ?0.5 v cc + 0.2 v common-mode range v cc = 2.5 v to 5.5 v ?0.2 v cc + 0.2 v differential voltage v cc = 2.5 v to 5.5 v v cc + 0.8 v offset voltage v os ?5.0 2 +5.0 mv bias current i p , i n ?5.0 2 +5.0 a offset current ?2.0 2.0 a capacitance c p , c n 1.0 pf resistance, differential mode ?0.5 v to v cc + 0.2 v 200 700 k resistance, common mode ?0.2 v to v cc + 0.2 v 100 350 k active gain a v 85 db v cci = 2.5 v, v cco = 2.5 v, v cm = ?0.2 v to +2.7 v 50 db common-mode rejection ratio cmrr v cci = 5.5 v, v cco = 5.5 v, v cm = ?0.2 v to +5.7 v 50 db hysteresis r hys = 0.1 mv latch enable pin characteristics v ih hysteresis is shut off 2.0 v cc v v il latch mode guaranteed ?0.2 +0.4 +0.8 v i ih v ih = v cc ?6 +6 a i ol v il = 0.4 v ?0.1 ma hysteresis mode and timing hysteresis mode bias voltage current sink ?1 a 1.145 1.25 1.35 v resistor value hysteresis = 120 mv 65 80 95 k hysteresis current hysteresis = 120 mv ?18 ?14 ?10 a latch setup time t s v od = 50 mv ?2.0 ns latch hold time t h v od = 50 mv 2.0 ns latch-to-output delay t ploh , t plol v od = 50 mv 30 ns latch minimum pulse width t pl v od = 50 mv 23 ns shutdown pin characteristics v ih comparator is operating 2.0 v cco v v il shutdown guaranteed ?0.2 +0.4 +0.6 v i ih v ih = v cc ?6 +6 a i ol v il = 0 v ?80 a sleep time t sd i out < 0.5 ma 20 ns wake-up time t h v od = 100 mv, output valid 50 ns dc output characteristics v cco = 2.5 v to 5.5 v output voltage high level v oh i oh = 8 ma v cco = 2.5 v v cc ? 0.4 v output voltage high level ?40c v oh i oh = 6 ma v cco = 2.5 v v cc ? 0.4 v output voltage low level v ol i ol = 8 ma, v cco = 2.5 v 0.4 v output voltage low level ?40c v ol i ol = 6 ma, v cco = 2.5 v 0.4 v
adcmp603 rev. 0 | page 4 of 16 parameter symbol conditions min typ max unit ac performance 1 rise time /fall time t r /t f 10% to 90%, v cco = 2.5 v 2.2 ns 10% to 90%, v cco = 5.5 v 4.5 ns propagation delay t pd v od = 50 mv, v cco = 2.5 v 3.5 ns v od = 50 mv, v cco = 5.5 v 4.8 ns v od = 10 mv, v cco = 2.5 v 5 ns propagation delay skewrising to falling transition t pinskew v cco = 2.5 v to 5.5 v v od = 50 mv 500 ps propagation delay skewq to qb t diffskew v cco =2.5 v to 5.5 v v od = 50 mv 300 ps overdrive dispersion 10 mv < v od < 125 mv 1.5 ns common-mode dispersion ?2 v < v cm < v cci + 2 v v od = 50 mv 200 ps minimum pulse width pw min v cci = v cco = 2.5 v pw out = 90% of pw in 3.3 ns v cci = v cco = 5.5 v pw out = 90% of pw in 5.5 ns power supply input supply voltage range v cci 2.5 5.5 v output supply voltage range v cco 2.5 5.5 v positive supply differential v cci ? v cco operating ?3.0 +3.0 v positive supply differential v cci ? v cco nonoperating ?5.5 +5.5 v input section supply current i vcci v cci = 2.5 v to 5.5 v 1.1 1.8 ma output section supply current i vcco v cci = 2.5 v to 5.5 v 2.3 3.5 ma power dissipation p d v cc = 2.5 v 9 11 mw p d v cc = 5.5 v 21 30 mw power supply rejection ratio psrr v cci = 2.5 v to 5.5 v ?50 db shutdown mode supply current v cc =2.5 v 290 430 a 1 v in = 100 mv square in put at 50 mhz, v cm = 0 v, c l = 5 pf, v cci = v cco = 2.5 v, unless otherwise noted.
adcmp603 rev. 0 | page 5 of 16 timing information figure 2 illustrates the adcmp603 latch timing relationships. table 2 provides definitions of the terms shown in figure 2. 1.1v 50% v n v os differential input voltage latch enable q output t h t pdl t ploh t f v in v od t s t pl 05915-023 50% q output t pdh t plol t r figure 2. system timing diagram table 2. timing descriptions mbol timing description t input to output high delay propagation delay measured from the time th e input signal crosses the reference ( the input offset voltage) to the 50% point of an output low-to-high transition. pdh t input to output low delay propagation delay measured from the time th e input signal crosses the reference ( the input offset voltage) to the 50% point of an output high-to-low transition. pdl t latch enable to output high delay propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output low-to-high transition. ploh t latch enable to output low delay propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output high-to-low transition. plol t minimum hold time minimum time after the negative transition of the latch enable signal that the input signal must remain unchanged to be ac quired and held at the outputs. h t minimum latch enable pulse width minimum time that the latch enable signal must be high to acquire an input signal change. pl t minimum setup time minimum time before the negative transition of the latch enable signal occurs that an input signal change must be present to be acquired and held at the outputs. s t output rise time amount of time required to transition from a low to a high output as measured at the 20% and 80% points. r t output fall time amount of time required to transition from a high to a low output as measured at the 20% and 80% points. f v voltage overdrive difference between the input voltages v od a and v . b
adcmp603 rev. 0 | page 6 of 16 absolute maximum ratings table 3. parameter rating stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. supply voltages input supply voltage (v to gnd) ?0.5 v to +6.0 v cci ?0.5 v to +6.0 v output supply voltage (v to gnd) cco ?6.0 v to +6.0 v positive supply differential (v ? v ) thermal resistance cci cco input voltages ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. input voltage ?0.5 v to v + 0.5 v cci differential input voltage (v + 0.5 v) cci table 4. thermal resistance maximum input/output current 50 ma shutdown control pin package type unit ja 1 applied voltage (hys to gnd) ?0.5 v to v cco + 0.5 v adcmp603 lfcsp 12-lead 62 c/w 1 measurement in still air. maximum input/output current 50 ma esd caution latch/hysteresis control pin applied voltage (hys to gnd) ?0.5 v to v cco + 0.5 v maximum input/output current 50 ma output current 50 ma temperature operating temperature, ambient ?40c to +125c operating temperature, junction 150c storage temperature range ?65c to +150c
adcmp603 rev. 0 | page 7 of 16 pin configuration and fu nction descriptions pin 1 indicator 1v cco 2v cci 3v ee 9v ee 8le/hys 7s dn 4 v p 5 v e e 6 v n 1 2 q 1 1 v e e 1 0 q top view (not to scale) adcmp603 05915-002 figure 3. adcmp603 pin configuration table 5. pin function descriptions pin no. mnemonic description 1 v output section supply. cco 2 v cci input section supply. 3 v ee negative supply voltage. 4 v p noninverting analog input. 5 v ee negative supply voltage. 6 v n inverting analog input. 7 s dn shutdown. drive this pin low to shut down the device. 8 le/hys latch/hysteresis control. bias with resistor or current for hysteresis adjustment; drive low to latch. 9 v ee negative supply voltage. 10 q inverting output. q is at logic low if the analog voltage at the noninverting input, v p , is greater than the analog voltage at the inverting input, v n , if the comparator is in compare mode. see the le/hys pin description (pin 8) for more information. 11 v ee negative supply voltage. 12 q noninverting output. q is at logic high if th e analog voltage at the noninverting input, v p , is greater than the analog voltage at the inverting input, v n , if the comparator is in compare mode. see the le pin description (pin 8) for more information. v heat sink paddle the metallic back surface of the package is electrically connected to v ee ee . it can be left floating because pin 3, pin 5, pin 9, and pin 11 provide adequate electrical connection . it can also be soldered to the application board if improved thermal and/or mechanical stability is desired. exposed metal at package corners is connected to the heat sink paddle.
adcmp603 rev. 0 | page 8 of 16 typical performance characteristics v cci = v cco = 2.5 v, t = 25c, unless otherwise noted. a 4 1 2 3 0 ?1 ?2 ?5 0 5 10 15 20 05915-010 typical output voltage (v) load current (ma) output voltage ?800 ?101234 567 ?600 ?400 ?200 0 200 400 600 800 05915-007 current (a) le/hysteresis pin voltage (v) v cc = 5.5v v cc = 2.5v figure 4. le/hys pin i/v curve figure 7. v vs. load current ol 50 150 250 350 450 550 650 05915-004 hysteresis (mv) hysteresis resistor (k ? ) 1 10 100 1000 v cc = 5.5v v cc = 2.5v 05915-006 current (a) shutdown pin voltage (v) ?1 7 6543210 ?150 150 ?100 100 ?50 50 0 200 v cc = 2.5v v cc = 5.5v figure 5. s pin i/v curve figure 8. hysteresis vs. r dn hys 05915-005 i b (a) common-mode voltage (v) ?20 ?15 15 ?10 10 ?5 5 0 20 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 i b @ +125c i b @ +25c v cc = 2.5v i b @ ?40c 0 ?2 ?4 ?6 ?8 ?10 ?12 ?14 ?16 ?18 05915-003 hysteresis (mv) hysteresis pin current (a) 0 50 100 150 200 250 300 350 hysteresis @ +125c hysteresis @ +25c hysteresis @ ?40c figure 9. hysteresis vs . hysteresis pin current figure 6. input bias current vs. input common mode
adcmp603 rev. 0 | page 9 of 16 8 7 6 5 4 2 3 05915-009 propagation delay (ns) overdrive (mv) 0 10 20 30 40 50 60 70 80 90 100 110 120 140130 05915-024 500mv/div m2.00ns figure 10. propagation delay vs. input overdrive figure 12. 50 mhz output voltage waveform at v cco = 2.5 v ?0.6 0 0.6 1.2 1.8 2.4 3.0 4.0 3.8 3.6 3.4 3.2 3.0 05915-008 delay (ns) common-mode voltage (v) prop delay rise ns prop delay fall ns v cc = 2.5v 05915-025 1.00v/di v m2.00ns figure 13. 50 mhz output voltage waveform at v figure 11. propagation delay vs. input common mode cco = 5.5 v
adcmp603 rev. 0 | page 10 of 16 application information power/ground layout and bypassing this delay is measured to the 50% point for the supply in use; therefore, the fastest times are observed with the v cc supply at 2.5 v, and larger values are observed when driving loads that switch at other levels. the adcmp603 comparator is a very high speed device. despite the low noise output stage, it is essential to use proper high speed design techniques to achieve the specified performance. because comparators are uncompensated amplifiers, feedback in any phase relationship is likely to cause oscillations or undesired hysteresis. of critical importance is the use of low impedance supply planes, particularly the output supply plane (v when duty cycle accuracy is critical, the logic being driven should switch at 50% of v cc and load capacitance should be minimized. when in doubt, it is best to power v cco or the entire device from the logic supply and rely on the input psrr and cmrr to reject noise. cco ) and the ground plane (gnd). individual supply planes are recommended as part of a multilayer board. providing the lowest inductance return path for switching currents ensures the best possible performance in the target application. overdrive and input slew rate dispersions are not significantly affected by output loading and v cc variations. the ttl-/cmos-compatible output stage is shown in the simplified schematic diagram (figure 14). because of its inherent symmetry and generally good behavior, this output stage is readily adaptable for driving various filters and other unusual loads. it is also important to adequately bypass the input and output supplies. multiple high quality 0.01 f bypass capacitors should be placed as close as possible to each of the v cci and v cco supply pins and should be connected to the gnd plane with redundant vias. at least one of these should be placed to provide a physically short return path for output currents flowing back from ground to the v output q2 q1 + in ? in output stage v logic gain stage a2 a1 a v 0 5915-012 cco pin. high frequency bypass capacitors should be carefully selected for minimum inductance and esr. parasitic layout inductance should also be strictly controlled to maximize the effectiveness of the bypass at high frequencies. if the input and output supplies have been connected separately such that v cci v cco , care should be taken to bypass each of these supplies separately to the gnd plane. a bypass between them is futile and defeats the purpose of having separate pins. it is recommended that the gnd plane separate the v cci and v cco planes when the circuit board layout is designed to minimize coupling between the two supplies and to take advantage of the additional bypass capacitance from each respective supply to the ground plane. this enhances the performance when split input/output supplies are used. if the input and output supplies are connected together for single-supply operation such that v figure 14. simplified schematic diagram of ttl-/cmos-compatible output stage cci = v using/disabling the latch feature cco , coupling between the two supplies is unavoidable; however, careful board placement can help keep output return currents away from the inputs. the latch input is designed for maximum versatility. it can safely be left floating for fixed hysteresis or be tied to v cc to remove the hysteresis, or it can be driven low by any standard ttl/cmos device as a high speed latch. ttl-/cmos-compatible output stage specified propagation delay performance can be achieved only by keeping the capacitive load at or below the specified minimums. the low skew complementary outputs of the adcmp603 are designed to directly drive one schottky ttl or three low power schottky ttl loads or the equivalent. for large fan outputs, buses, or transmission lines, use an appropriate buffer to maintain the excellent speed and stability of the comparator. in addition, the pin can be operated as a hysteresis control pin with a bias voltage of 1.25 v nominal and an input resistance of approximately 7000 , allowing the comparator hysteresis to be easily controlled by either a resistor or an inexpensive cmos dac. hysteresis control and latch mode can be used together if an open drain, an open collector, or a three-state driver is connected parallel to the hysteresis control resistor or current source. with the rated 5 pf load capacitance applied, more than half of the total device propagation delay is output stage slew time, even at 2.5 v v due to the programmable hysteresis feature, the logic threshold of the latch pin is approximately 1.1 v regardless of v cc . cc . because of this, the total prop delay decreases as v cco decreases, and instability in the power supply may appear as excess delay dispersion.
adcmp603 rev. 0 | page 11 of 16 q/q output input voltage 10v/ns 1v/ns dispersion v n v os 05915-014 optimizing performance as with any high speed comparator, proper design and layout techniques are essential for obtaining the specified performance. stray capacitance, inductance, inductive power and ground impedances, or other layout issues can severely limit performance and often cause oscillation. large discontinuities along input and output transmission lines can also limit the specified pulse- width dispersion performance. the source impedance should be minimized as much as is practicable. high source impedance, in combination with the parasitic input capacitance of the comparator, causes an undesirable degradation in bandwidth at the input, thus degrading the overall response. thermal noise from large resistances can easily cause extra jitter with slowly slewing input signals; higher impedances encourage undesired coupling. figure 16. propagation delayslew rate dispersion comparator hysteresis the addition of hysteresis to a comparator is often desirable in a noisy environment, or when the differential input amplitudes are relatively small or slow moving. figure 17 shows the transfer function for a comparator with hysteresis. as the input voltage approaches the threshold (0.0 v, in this example) from below the threshold region in a positive direction, the comparator switches from low to high when the input crosses +v comparator propagation delay dispersion the adcmp603 comparator is designed to reduce propagation delay dispersion over a wide input overdrive range of 5 mv to v h /2, and the new switching threshold becomes ?v h /2. the comparator remains in the high state until the new threshold, ?v cci C 1 v. propagation delay dispersion is the variation in propagation delay that results from a change in the degree of overdrive or slew rate (that is, how far or how fast the input signal exceeds the switching threshold). h /2, is crossed from below the threshold region in a negative direction. in this manner, noise or feedback output signals centered on 0.0 v input cannot cause the comparator to switch states unless it exceeds the region bounded by v h /2. propagation delay dispersion is a specification that becomes important in high speed, time-critical applications, such as data communication, automatic test and measurement, and instru- mentation. it is also important in event-driven applications, such as pulse spectroscopy, nuclear instrumentation, and medical imaging. dispersion is defined as the variation in propagation delay as the input overdrive conditions are changed (figure 15 and figure 16). output input 0 v ol v oh +v h 2 ?v h 2 05915-015 adcmp603 dispersion is typically < 2 ns as the overdrive varies from 10 mv to 125 mv. this specification applies to both positive and negative signals because the device has very closely matched delays for both positive-going and negative-going inputs. figure 17. comparator hysteresis transfer function q/q output input voltage 500mv overdrive 10mv overdrive dispersion v n v os 05915-013 the customary technique for introducing hysteresis into a comparator uses positive feedback from the output back to the input. one limitation of this approach is that the amount of hysteresis varies with the output logic levels, resulting in hysteresis that is not symmetric about the threshold. the external feedback network can also introduce significant parasitics that reduce high speed performance and induce oscillation in some cases. figure 15. propagation delayoverdrive dispersion
adcmp603 rev. 0 | page 12 of 16 05915-026 50 150 250 350 450 550 650 hysteresis (mv) hysteresis resistor (k ? ) 1 10 100 1000 v cc = 5.5v v cc = 2.5v the adcmp603 comparator offers a programmable hysteresis feature that can significantly improve accuracy and stability. connecting an external pull-down resistor or a current source from the le/hys pin to gnd varies the amount of hysteresis in a predictable, stable manner. leaving the le/hys pin disconnected or driving it high removes the hysteresis. the maximum hysteresis that can be applied using this pin is approximately 160 mv. figure 18 illustrates the amount of hysteresis applied as a function of the external resistor value, and figure 9 illustrates hysteresis as a function of the current. the hysteresis control pin appears as a 1.25 v bias voltage seen through a series resistance of 7 k 20% throughout the hysteresis control range. the advantages of applying hysteresis in this manner are improved accuracy, improved stability, reduced component count, and maximum versatility. an external bypass capacitor is not recommended on the hys pin because it impairs the latch function and often degrades the ji tter performance of the device. as described in the using/disabling the latch feature section, hysteresis control need not compromise the latch function. figure 18. hysteresis vs. r control resistor hys minimum input slew rate requirement with the rated load capacitance and normal good pc board design practice, as discussed in the optimizing performance section, these comparators should be stable at any input slew rate with no hysteresis. broadband noise from the input stage is observed in place of the violent chattering seen with most other high speed comparators. with additional capacitive loading or poor bypassing, more persistent oscillations are seen. this oscillation is due to the high gain bandwidth of the comparator in combination with feedback parasitics in the package and pc board. in many applications, chattering is not harmful since the first cycle of the oscillation occurs close to v crossover bias point in both op amps and comparators, rail-to-rail inputs of this type have a dual front-end design. certain devices are active near the v cc rail and others are active near the v ee rail. at some predeter- mined point in the common-mode range, a crossover occurs. at this point, typically v cc /2, the direction of the bias current reverses and the measured offset voltages and currents change. os . the adcmp603 slightly elaborates on this scheme. crossover points can be found at approximately 0.8 v and 1.6 v.
adcmp603 rev. 0 | page 13 of 16 typical application circuits adcmp603 output + ? 5 v 0.1f 10k ? 10k ? input v ref 05915-020 0.02f le/hys adcmp603 cmos output 0.1f 2.5v to 5 v 0.1f 2k ? 2k ? input 05915-017 figure 22. duty cycle to differential voltage converter figure 19. self-biased, 50% slicer adcmp603 2.5v to 5 v 10k ? le/hys digital input hysteresis current 74 ahc 1g07 0 5915-022 adcmp603 cmos v dd 2.5v to 5v 100 ? lvds 05915-018 cmos output figure 23. hysteresis adjustment with latch figure 20. lvds-to-cmos receiver cmos pwm output adcmp603 2.5 v input 1.25v ref input 1.25v 50m v le/hys adcmp601 82pf 10k ? 10k ? 100k ? 10k ? 05915-021 le/hys adcmp603 5 v 150pf 10k ? 150k ? 10k ? 150k ? control voltage 0v to 2.5v 05915-019 output figure 24. oscillator and pulse-width modulator figure 21. voltage-controlled oscillator
adcmp603 2 rev. 0 | page 14 of 16 outline dimensions * compliant to jedec standards mo-220-veed-1 except for exposed pad dimension. 1 0.50 bsc 0.60 max pin 1 indicator 0.75 0.55 0.35 0.25 min 0.45 top view 12 max 0.80 max 0.65 typ pin 1 indicator 1.00 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref * 1.45 1.30 sq 1.15 12 4 10 6 7 9 3 2.75 bsc sq 3.00 bsc sq 2 5 8 11 coplanarity 0.08 exposed pad (bottom view) seating plane figure 25. 12-lead lead frame chip scale package [lfcsp_vq] 3 mm 3 mm body, very thin quad (cp-12-1) dimensions shown in millimeters ordering guide model temperature range package desc ription package option branding adcmp603bcpz-wp ?40c to +125c 12-lead lead frame chip scale package [lfcsp_vq] cp-12-1 g0d 1 ADCMP603BCPZ-R2 ?40c to +125c 12-lead lead frame chip scale package [lfcsp_vq] cp-12-1 g0d 1 adcmp603bcpz-r7 ?40c to +125c 12-lead lead frame chip scale package [lfcsp_vq] cp-12-1 g0d 1 z = pb-free part. 1
adcmp603 rev. 0 | page 15 of 16 notes
adcmp603 2 rev. 0 | page 16 of 16 notes ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05915-0-10/06(0)

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